December 1, 2012

What TIME is it?

WARNING: This post contains knowledge. Knowledge is injurious to happiness.


My circuits often fail with consumption of ethanol based solutions. So, I began to investigate why was I getting "slow". At times, with consumption of caffeine based fuels, I gain the abilities of a klutz. Investigation ensued to comprehend why my boards were "fast".

It was simple enough, Setup and Hold timings. I must say, a lot of people go through electronic engineering without knowing what those terms truly mean. I was one of them. Let's get straight to business shall we and hence, lets get some basics out of the way.

This is what you probably think a modern D-flip flop looks like, right?
Shoot yourself in the head with a sawed-off gauge 12.

Alright, now that we have cleared what you knew was wrong, these are the basic building blocks of the cmos flip flop:

Yes, a few inverters and transmission gates are all that you need. I'm not going to explain the working of an inverter and transmission gates. If you did not know that... shame. 
AND!, this is what a D-FF looks like:
Pay careful attention to the CLK and !CLK signals. The closed positive feedback loop created by keeping two inverters back to back is what truly "holds the state".
The transmission gates work in the following way:
  • txDW allows a signal at CLK =0
  • txZW allows a signal at CLK = 1
  • txXM allows a signal at CLK = 1
  • txPM allows a signal at CLK = 0
  • At all other conditions, all tx show a Z (high impedance)

Lets analyze the working. Say, at the beginning of time, before "God" took his seven days, Q is a 1 and there are no CLK signals (ie: CLK = 0). Working backwards, and in order,
  • invMN. in = 0 and out = 1
  • invOP, in = 1 and out = 0
  • txPM is open.
  • Positive feedback loop exists between invMN and invOP and Q = 1 persists.
  • txXM is closed
  • No one gives a damn whats before txXM, as it's closed.
How did Q get 1?! Well, it had to obviously come from D. That also means that  the CLK had to pulse, ie: go from 0 to 1 and back down again, 1 to 0 after a while. There are three moments in time that we must consider.
  1. Initial, CLK = 0
  2. Pulse, CLK = 1
  3. Rest, CLK = 0
PS: At all times, D = 1. Below, CYAN highlighted loops are those that are driven by a signal. RED loops are in positive feedback.

Initial : CLK=0



  • txDW is open! 
  • invWX, in = 0 (from D) and out = 1
  • invYZ, in = 1 and out = 0
  • txZW is closed. No loop exists, but there is direct signal drive from D
  • When CLK = 0, what happens in the MNOP loop has already been discussed. Don't you pay any attention?
Conclusion: point X is at 0


Pulse: CLK=1


  • txDW closes.
  • txZW opens!
  • Positive feedback loop now exists in WXYZ (Drive from D is cut off by txDW, loop enabled by txZW). As previous, the logic at point X is 0 and it persists.
  • txXM is open! and drives the loop MNOP.
  • Looking at loop MNOP,
    • invMN, in = 0 and out = 1
    • invOP, in = 1 and out = 0
    • txPM is closed
    • Q remains at 1 as the drive is provided by the positive feedback loop WXYZ, via txXM
Conclusion: Now, we know how Q got its logic 1. Yay!

Rest: CLK=1024mod2


  • txDW opens!
  • And we go back to how it was at the Inital state. The loop is broken by txZW, which is closed and the drive is provided by signal D.
  • txXM closed, and txPM opens.
  • This enables the positive feedback loop MNOP and... here's the finale... Q=1 persists.
Conclusion: We now know what a D-FF truly looks like and how it works. Throw rocks at people who keep telling you that flip flops are entirely made of NAND gates.

What's this got to do with Setup and Hold?!

Well, realistically, D doesn't remain at 1 forever and CLK keeps pulsating throughout time regardless of D. In real-life, there's a finite time for TX gates and inverters to change their state... gate capacitiances and oher parasitics need to be charged/discharged. 

It is here that I introduce the concept of SETUP and HOLD. 
Setup time is a timing parameter associated with Sequential Devices (for simplicity henceforth I will be only referring to the Flip Flop). The Setup time is used to meet the minimum pulse width requirement for the first (Master) latch in the  flip flop. More simply, the setup time is the amount of time that an input signal (to the device) must be stable (unchanging) before the clock ticks in order to guarantee minimum pulse width and thus avoid possible metastability.
Basically, This is about the Initial state and the loop WXYA (henceforth shall be called the Master Latch). In our example D has been stable since the beginning of time... In real-life, it isn't. A finite amount of time is required for txDW, invWX and invYZ to shift their states and reach Initial. If D changed during this time, well... we would have no idea what state the Master Latch would be in .
This finite time required by the Master Latch to latch-on to the incoming data signal BEFORE the transition of the clock is called... SETUP.

Hold time is also a timing parameter associated with Flip Flops and all other sequential devices. The Hold time is used to further satisfy the minimum pulse width requirement for the first (Master) latch that makes up a flip flop. The input must not change until enough time has passed after the clock tick to guarantee the master latch is fully disabled. More simply, hold time is the amount of time that an  input signal (to  a sequential device) must be stable (unchanging)  after the clock tick in order to guarantee minimum pulse width and thus avoid possible metastability

I couldn't have explained HOLD better myself. As discussed before, txDW closes at CLK = 1, which enables the positive feedback loop in WXYZ, also known as latching of the Master Latch. A finite amount of time is required by txDW to close. This is our HOLD time.

As usual, HOLD time requirements are far smaller than SETUP as HOLD is only dependent on the closing of the first TX gate of the Master Latch, while SETUP depends on the Master Latch getting ready to latch.

One must also consider the timing boundary between the Master and Slave latch. The Master must satisfy the SETUP and HOLD requirements of the Slave latch. This where we consider minimum pulse width... ie, an upper limit on how fast your clock can be. Well, it can't be too fast that the Master switches states even before the Slave has enough time to latch on to it. All of timing analysis is technology dependent. CMOS has a lot of parasitics that we need to consider.

Can I have my beer, now?